1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a data recovery circuit.
2. Description of the Related Art
A semiconductor apparatus including double data rate synchronous DRAM (DDR SDRAM) performs various operation in response to external data and a clock. The dock is used for various purposes within the semiconductor apparatus, but is specially used to synchronize data. Accordingly, a corresponding high-speed clock is necessary to process high-speed data. It is, however, very difficult to transmit the high-speed data and the high-speed clock from a transmission circuit to a reception circuit at the same time and to minutely control the timing. Thus, with advances in technology, only data is transmitted and recovered without transmitting both data and a clock. A circuit for enabling this transmission operation is a data recovery circuit.
FIGS. 1 and 2 are timing diagrams illustrating an overall operation of a typical data recovery circuit. An example that 10 data DAT is inputted as one set is described below, for purpose of description.
FIG. 1 shows 10 edge clocks CLK_E and 10 data docks CLK_D corresponding to the respective data DAT. The 10 edge clocks CLK_E are clocks to be placed at the points of time at which the respective data DAT shift, and the 10 data clock CLK_D are clocks to be placed in the middle of the respective data DAT.
The edge clocks CLK_E and the data clocks CLK_D that are internally generated may not be placed at the points of time at which the data DAT shifts and in the middles of the data DAT when being initially generated. Accordingly, the edge clocks CLK_E are first controlled through a locking operation so that the edge clocks CLK_E can be placed at the points of time at which the data DAT shifts. The locking operation means an operation of detecting points of time at which the data DAT shifts and controlling the edge clocks CLK_E to be placed at the points of time at which the data DAT shifts. Since the data clock CLK_D is generated to have a specific phase difference from the edge clock CLK_E, the data clocks CLK_D are naturally placed in the middles of the data DAT when the locking operation is completed. Accordingly, when the locking operation is completed, a data recovery circuit may sample the data DAT in response to the data clock CLK_D and perform a data recovery operation.
On the other hand, the data DAT does not always have a data value that continues to toggle/oscillate like a clock. That is, as shown in FIG. 2, sections {circle around (1)} and {circle around (2)} in which the same data value as a previous data value is maintained may be generated in the 10 data DAT. Accordingly, in the sections {circle around (1)} and {circle around (2)} in which the shift operation of the datum DAT is not performed, a locking operation, which is an operation of detecting a point of time at which the datum DAT shifts and an operation of controlling the phase of the edge clock CLK_E, is meaningless.
As described above, in order to recover the data DAT, a plurality of the edge clocks CLK_E and a plurality of the data clocks CLK_D are used. To this end, a clock generation circuit for generating the plurality of edge clocks CLK_E and the plurality of data clocks CLK_D is to be included in the data recovery circuit. However, since the clock generation circuit occupies a relatively wide area and consumes relatively great power, it may become a burden on circuit design of the data recovery circuit. Furthermore, an operation of controlling phases is to be performed on the plurality of edge clocks CLK_E and the plurality of data clocks CLK_D. Here, when taking into consideration the area of a circuit for the operation of controlling phases, a burden on the design of the data recovery circuit may inevitably increase.